FPGA Design Services

Whether Altera, Xilinx, Microsemi/Actel or Lattice, the FPGA design process has become similar to that of ASIC’s. This is largely due to the evolution of System on a Programmable Chip (SOPC) technologies, including significant increases in gate count, memory densities and the emergence of IP. When IP is used, unique verification and synthesis challenges can arise. Anticipating these up front will allow the design cycle to proceed smoothly and within schedule. Our services range from augmenting your team in one specific area to supporting the entire project development cycle. Integre’s FPGA services include:

Design Evaluation and Requirements

  • Specification generation
  • Architecture definition
  • Identifying IP requirements (if any)
  • Vendor and device selection
  • Tool selection
  • Verification Strategy

Design and Verification

  • RTL design
  • VHDL, Verilog
  • RTL Verification (Verification)
  • Synthesis
  • Static Timing Analysis
  • Gate level verification

By following a disciplined approach along with close interaction with the customer throughout the design cycle, Integre Technologies brings success to every design. Our approach to RTL design is hierarchical in nature to help ensure maintainability and reuse.


You can have confidence that Integre Technologies has the required experience to handle your FPGA designs. The Integre staff has successfully delivered hundreds of designs for commercial and defense applications, including ground, air and space based products.


   Intel/Altera Quartus II Design Software

   Intel/Altera SoC Embedded Design Suite

   Intel/Altera Qsys

   Intel/Altera SOPC Builder

   Intel/Altera SignalTap

   Xilinx Vivado Design Suite  

   Xilinx ISE Design Suite

   Xilinx ChipScope

   Microsemi/Actel Libero IDE

   Lattice IspLEVER Design Software

   Lattice Diamond Design Software

   Lattice Reveal Analyzer

   Exemplar / Mentor Precision Synthesis

   Mentor Leonardo Spectrum

   Mentor ModelSim

   Synplicity/Synopsys Synplify

   Mentor QuestaSim