FPGA Connection Review
The FPGA Connections / Schematic review is a short duration, time bounded and fixed price engagement that evaluates a new or existing design to:
- Analyze the FPGA pin assignments
- Review schematic connectivity, power and ground partitioning
- Ensure FPGA related layout rules are identified
- Review schematic for proper termination
- Identify potential issues and recommend changes
At the end of the Design Evaluation project you will have a high confidence that the FPGA is properly connected and the PCB is properly specified.
Schematic Design Evaluation
The Schematic Design Evaluation is a time bounded and fixed price engagement that evaluates a new or existing design to:
- Analyze Programmable Logic pin assignments
- Analyze connector pin assignments
- Review schematic connectivity, power and ground partitioning
- Identify potential ESD/EMI issues and solutions
- Review analog/digital design partitioning
- Review test accessible signals
- Ensure board layout rules are identified
- Review schematic for proper termination
- Identify potential issues and recommend changes
At the end of the Schematic Design Evaluation you will have a high confidence that your board design is properly connected and partitioned.
ASIC Design Evaluation
The ASIC Design Evaluation is a short duration project that engages Integre experts with the client team accelerating the ASIC development curve by rapidly answering questions in the following key project areas:
- Architecture
- Specification
- Foundry Selection
- Schedule Estimate
- Cost Estimate – labor and tools
At the end of the ASIC Design Evaluation your team will have a solid foundation enabling them to make the project and architectural tradeoff decisions which are required at the end of the ASIC Design Specification Phase. You will know: