Whether Altera, Xilinx, Actel or Lattice, the FPGA design process has become similar to that of ASIC's. This is largely due to the evolution of System on a Programmable Chip (SOPC) technologies, including significant increases in gate count, memory densities and the emergence of IP. When IP is used, unique verification and synthesis challenges can arise. Anticipating these up front will allow the design cycle to proceed smoothly and within schedule. Our services range from augmenting your team in one specific area to supporting the entire project development cycle. Integre’s FPGA services include:

Design Evaluation and Requirements

• Specification generation
• Architecture definition
• Identifying IP requirements (if any)
• Vendor and device selection
• Tool selection
• Verification Strategy

Design and Verifiction

• RTL design
• VHDL, Verilog
• RTL Verification (Verification)
• Synthesis
• Static Timing Analysis
• Gate level verification

By following a disciplined approach along with close interaction with the customer throughout the design cycle, Integre Technologies brings success to every design. Our approach to RTL design is hierarchical in nature to help ensure maintainability and reuse.