FPGA Design Services

Whether Altera, Xilinx or Actel processes used to design FPGA's have become similar to those of ASIC's. This is largely due to the evolution of System on a Programmable Chip (SOPC) technologies, including significant increases in gate count, memory densities and the emergence of IP. When IP is used, unique verification and synthesis challenges can arise. Anticipating these up front will allow the design cycle to proceed smoothly and within schedule. A system level approach to verification test benches can be incorporated which may include the interaction of multiple FPGA’s. RTL design will be hierarchical in nature to help ensure maintainability and reuse. Integre offers a disciplined process for developing FPGA's including:

• Specification generation
• Architecture definition
• Identifying IP requirements if necessary
• Vendor and device selection
• Tool selection• Verification strategy
• RTL design and verification
• Synthesis
• Post Synthesis verification