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Integre Senior Scientist published in EE times online
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Integre Technologies Selected As Texas Instruments Authorized Design Center -
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Integre Technologies Announces PCIExpress™ Verification Services - Click here

Careers

 

Integre Technologies is always interested in considering talented engineers. We are currently seeking:

Title:    Digital ASIC Design Engineer

Job Description

We are seeking a highly productive person able to contribute as an individual and work within a distributed team. Create timing constraints and perform static timing analysis to ensure device works to specification. You will work closely with the ASIC design team to ensure tapeout success. Applicants must have experience using the tools associated with STA and Synthesis including Synopsys Primetime, Design Compiler and exposure to Magma BlastFusion a plus.

Requirements

  • BSEE or MSEE (preferred)
  • Minimum 5 years of experience with ASIC design and /or verification
  • Experience setting up, running and analyzing STA reports.
  • Ability to review specifications to understand design constraints and then able to apply these to timing constraints
  • Ability to debug constraint and timing issues
  • Understanding of ASIC test operational modes such as ATPG, BIST, DFT
  • Experience with RTL languages including Verilog and VHDL
  • Experience with scripting languages including Perl and TCL
  • Experience with revision control software, Clearcase a plus
  • Experienced in writing and presentation of technical proposals and project status.
  • Excellent communication skills and ability to work with a diverse set of clients
  • Some travel required

Compensation

We offer a competitive salary based on experience, 401K program plus medical, dental and vision benefits along with a pleasant work environment.

 

Please send resumes for consideration to:
recruiting@integretek.com

Title:    Verification Engineer

Job Description

We are seeking a highly productive person able to contribute as an individual and work within a distributed team. Applicants must be able to participate in the development of verification test benches and infrastructure, create test plans, code and execute tests. Applicants must have experience using the design tools associated with ASIC verification, preferably Cadence tool experience.

Requirements

  • BSEE or MSEE (preferred)
  • Minimum 5 years of experience with ASIC design and /or verification
  • Working knowledge in all phases of the ASIC process (design through GDSII hand-off)
  • Experience with development of verification test plans and test benches
  • Ability to develop tests from a high level test description
  • Experience with RTL languages including Verilog and VHDL
  • Analog modeling and verification experience is desirable
  • Knowledge of and experience with ASIC verification languages including Specman, System C, Vera, C / C++ and scripting languages
  • Experienced in writing and presentation of technical proposals and project status.
  • Excellent communication skills and ability to work with a diverse set of clients
  • Some travel required

Compensation

We offer a competitive salary based on experience, 401K program plus medical, dental and vision benefits along with a pleasant work environment.

 

 


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