Integre Technologies Announces
PCIExpress™ Verification Services

Verification of
next generation serial bus

Rochester, NY – September 29, 2005 – Integre Technologies a leading provider of ASIC design and verification services today announced their PCIExpress™ verification service. This service is targeted to organizations develop ing
products with the PCIExpress interface.

“Our project experience allows us to avoid the pitfalls and risks of various tools and environments” states Mark Blejwas Integre Managing Partner. Whether we are engaged at the outset of the project or brought into an existing effort, our understanding of the intricacies of the PCIe™ architecture and the verification flow can save months of effort for a customer translating into a significantsavings in budget without sacrificing quality.”

PCI Express is a robust, scalable, flexible, cost-effective I/O interconnect that provides a significant increase in available bandwidth (500 MBps per lane -- dual-simplex) without requiring the system integrator to use more expensive PCB materials or to add layers to accommodate wider parallel buses. Each PCI Express lane supports 2.5 Gbps in each direction and can scale to support as many
as 32 lanes in a single link. Low-cost platforms can now provide enough bandwidth in the I/O backbone to support applications like SATA, Gigabit/10-Gbit Ethernet and 1394b.